The objective of this project is to design an operational amplifier (Op-amp) chip based on the given specifications. In this assignment, the Miller’s operational amplifier (Op-amp) is being implemented. The Miller Op-amp is chosen due to its simplicity and its ability to have a wider range of voltage swing as compared to the cascade or other Op-amp topology. However, the Miller Op-amp does have issues regarding with its stability. Nevertheless, the instability of the Miller Op-amp can be compensated by adding a resistor and capacitor combination in the design process. A high current of 70 µA is needed in order to have a faster settling time. This can be achieved with ease as the capacitor CGD of the common source amplifier will charge up faster. Hence, it will reduce the settling time. The compensation to stabilise the Miller Op-amp is achieved by adding a capacitor across the gate-drain of the common source amplifier to amplify the Miller’s effect. With the addition of this capacitor, the poles will be split further apart which in turn improves the phase margin. However, the capacitance of this compensation capacitor should not be too high as it will result in a longer settling time.